Patents

The patent covers a silicon solar cell formed on a highly-doped substrate with a two-layer epitaxially deposited emitter. Both layers of emitter have variable doping profile. The low-doped area adjacent to p-n-junction provides light absorbtion and the lighted highly-doped area is used to form contacts.

Substrate material can be mono- or multicrystalline silicon, both p- and n-type. The solar cell design developed by Epiel provides for improved efficiency.

The patent covers a method of forming semiconductor structures of Silicon and/or Germanium by depositing semiconductor material on a substrate by mass transfer over a small gap from a solid source material, for instance Silicon wafer, in Hydrogen environment with minimum source gas flow or in still atmosphere.

The method provides for substantially decreased production cost and can be used to manufacture epitaxial wafers for Discrete device, Integrated circuit and Solar cell applications.

SUBSTANCE: method for producing epitaxial layers of monocrystalline silicon of n- and p-type conductivity in a material of dielectric substrates with lattice parameters similar to parameters silicon by chemical vapour phase epitaxy. The substrate material may be used, in particular, leucosapphire (corundum), spinel, diamond, quartz.

The method consists in the location of the substrate in the reactor, heating the working surface of the substrate to 900-1000°C, the reaction gas feed stream comprising an inert carrier gas and monosilane silicon capacity to form an initial continuous layer on the working surface of the substrate, adding to the flow of the reaction gas a halogen-containing reactant stream and forming an epitaxial silicon layer of desired thickness. Starting solid silicon layer is increased at a rate of 3000 E/min to 6000 E/min. After forming the layer on the working surface of the substrate of the reaction gas flow rate is reduced, reducing the growth rate at 500-2000 E/min. To the flow of the reaction, the gas stream of saturated vapour of silicon halide or halosilane gas is added, whose flow rate is set so that the growth rate of the silicon layer returned to the values of 3000-6000 E/min.

EFFECT: obtaining high quality silicon layer and reducing the cost of the manufacturing process.

Inventor(s):

Sokolov Evgenij Makarovich (RU), Fedotov Sergej Dmitrievich (RU), Statsenko Vladimir Nikolaevich (RU), Timoshenkov Sergej Petrovich (RU)

Proprietor(s):

Epiel JSC (RU)

SUBSTANCE: device comprises two electrolytic probes, in which each body is represented in the form of a hollow transparent tube of the dielectric material, at one end of which a monolith tip of dielectric capillary or porous material is fixed in the form of a cone with an elongated cylindrical base , and at the other end a rubber plug is fixed. The device electrodes are rings of inert metal and are located on the outer surface of the conical tips. The material of the conical tips is impregnated with electrolyte, the probes are mounted on the measured plate by the conical tips along the normal to the front surface, DC voltage of different polarity is applied to the electrodes, DC voltage is gradually increased, and short periodic sinusoidal voltage pulses with an amplitude, greater than the DC voltage value, are simultaneously supplied to the measuring electrodes of the electrolytic probes. Current-voltage semiconductor characteristic is recorded by the output device of the radio devices.

EFFECT: increasing the measurement accuracy and expanding the application area.

Inventor(s):

Kochin Ruslan Nikolaevich (RU), Fedotov Sergej Dmitrievich (RU), Lublin Valeriy Vsevolodovich (RU), Shwarz Carl-Henrih Markusovich (RU)

Proprietor(s):

Epiel JSC (RU)

SUBSTANCE: method for producing heteroepitaxial silicon layer comprises formation of growth silicon islands on the surface of the dielectric substrate (sapphire, spinel, diamond, quartz) with subsequent build-up of initial silicon layer by thermal decomposition of monosilane, its heat treatment over a period of time sufficient for removing structural defects arising as a result of stress relaxation of silicon crystal lattice, and continuation of build-up of silicon layer to required thickness values. The build-up of initial silicon layer is carried out at a temperature of 930-945°C until merge of growth silicon islands and formation of a continuous layer, heat treatment temperature is set within 945-975°C, and the temperature of layer growth of the required thickness is set not less than 960°C.

EFFECT: increased structural quality and homogeneity of the resistivity distribution over the thickness of the heteroepitaxial silicon layer on the dielectric.

Inventor(s):

Fedotov Sergej Dmitrievich (RU), Sokolov Evgenij Makarovich (RU), Statsenko Vladimir Nikolaevich (RU), Timoshenkov Sergej Petrovich (RU)

Proprietor(s):

Epiel JSC (RU)